Printed Circuit Board Reliability Design - Decoupling Capacitor Configuration

In a DC power supply loop, changes in load can cause power supply noise. For example, in a digital circuit, when a circuit transitions from one state to another, a large spike current is generated on the power line to form a transient noise voltage. The configuration of decoupling capacitors can suppress the noise generated by load changes. It is a common practice for the reliability design of printed circuit boards. The configuration principles are as follows:

The power input terminal is connected to a 10~100uF electrolytic capacitor. If the position of the printed circuit board is allowed, the anti-interference effect of the electrolytic capacitor above 100uF is better. A 0.01 uF ceramic capacitor is provided for each integrated circuit chip. If you encounter a small printed circuit board space and can not fit, you can configure a 1 ~ 10uF tantalum electrolytic capacitor every 4 ~ 10 chips, the high-frequency impedance of this device is particularly small, the impedance is less than 1Ω in the range of 500kHz ~ 20MHz, Moreover, the leakage current is small (0.5 uA or less). For devices with weak noise capability, large current changes during shutdown, and memory devices such as ROM and RAM, decoupling capacitors should be directly connected between the power supply line (Vcc) and ground (GND) of the chip.

The leads of the decoupling capacitors must not be too long, especially if the high frequency bypass capacitors are not leaded.