Design Tips and Key Points for Efficient Automated Routing of PCBs (II)

3. Component layout

To optimize the assembly process, the Manufacturability Design (DFM) rules impose restrictions on component placement. If the assembly department allows components to move, the circuit can be properly optimized for easier automatic routing. The defined rules and constraints affect the layout design.

In the layout, you need to consider the routing channel and the via area, as shown in Figure 1. These paths and areas are obvious to the designer, but the automatic routing tool only considers one signal at a time. By setting the wiring constraints and setting the layers of the signal lines, the routing tools can be imagined by the designer. That completes the wiring.

4. Fanout design

In the fan-out design phase, for the auto-wiring tool to connect component leads, each pin of the surface mount device should have at least one via so that the board can perform the inner layer when more connections are needed. Connectivity, online testing (ICT) and circuit reprocessing.

In order to make the automatic routing tool the most efficient, it is necessary to use the largest via size and the printed wiring as much as possible, and the interval is preferably set to 50 mils. Use a via type that maximizes the number of routing paths. When performing fan-out design, consider the online test of the circuit. Test fixtures can be expensive and are usually ordered when they are ready for full production. It is too late to consider adding nodes to achieve 100% testability.

After careful consideration and prediction, the design of the circuit online test can be carried out at the beginning of the design, implemented in the later stage of the production process, and the type of via fanout is determined according to the wiring path and the circuit online test. The power supply and grounding also affect the wiring and fanout design. . To reduce the inductive reactance of the filter capacitor connection, the via should be placed as close as possible to the surface mount device pins. If necessary, manual routing can be used, which may affect the originally proposed routing path and may even cause you to re- Consider which via is used, so you must consider the relationship between via and pin inductance and set the priority of the via specification.